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The 22 nanometer (22 nm) node is the CMOS process step following 32 nm. It is expected to be reached by semiconductor companies in the 2011–2012 timeframe. At that time, the typical half-pitch for a memory cell would be around 22 nm. The exact naming of this technology node comes from the International Technology Roadmap for Semiconductors (ITRS).
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.
Since the 32 nm half-pitch already requires using double patterning, in conjunction with hyper-NA (numerical aperture) immersion lithography tools, this approach will continue to be used at the 22 nm half-pitch, to which it can be scaled.
Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as FinFETs). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface. As of late 2008, several technical risks remain for implementation of non-planar 22 nm transistors for logic applications.
According to the ITRS, the 22 nm node also marks the first time where the pre-metal dielectric, separating the transistor from the first metal layer, is a porous low-k material, replacing traditional, denser CVD silicon dioxide. The introduction of a porous material closer to the front end presents numerous integration challenges. In particular, the extent of plasma damage to low-k materials is typically 20 nm thick, but can also go up to approximately 100 nm.
On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 square μm. The cell was printed using immersion lithography.
The 22 nm node may indicate the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009 during the Intel Developer Forum Fall 2009, Intel showed 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm2, smallest reported to date.
On January 3, 2010 Intel Corp. and Micron Technology Inc. announced the first in a family of 25-nm NAND devices.
- ^ EEtimes article on 22 nm
- ^ http://www.semiconductor.net/article/CA6622435.html
- ^ O. Richard et al., Microelectronic Engineering 84, pp. 517-523 (2007).
- ^ T. Gross et al., Microelectronic Engineering 85, pp. 401-407 (2008).
- ^ TG Daily news report
- ^ EETimes news report
- ^ Intel announces 22nm chips for 2011
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